There are a myriad of precautionary measures to consider when executing sensitive current measurements with 1-channel DC-DC converters. Below is just one unwritten rule.
When performing inductor current measurement with the buck converter illustrated, at which side should the current probe be placed for stable (less noise-prone) oscilloscope plots?
Case I. After the inductor.
(the schematics are courtesy of Electronic Design with a few minor modifications)
Case I shows the probe after the inductor. At this side, voltage is DC with negligible ripple (if the output capacitor is chosen correctly). This is due to electromotive inertia provided by the capacitor when the high side FET/transistor is in cut-off. (Further evidence can be shown by taking state equations for all possible states of the FETs)
Looking at Case II, the probe is at the switching side of the converter's power stage. At this node, the voltage is switching (as both HFET and LFET turn on and off alternatingly - never at the same time - a gap existing called dead time to avoid a short from supply to ground). This switching is characterized by fast rise and fall times at high frequency (typically in the MHz range for mobile applications). Such undesirable voltage characteristics may affect measured current waveform, hence the more practical case (and the answer to our question) is Case I.
[There's an additional method pertaining to using shunt resistors being impractical because of possibility of switching noise coupling with the resistor. Inserting a resistor also introduces parasitics into the branch (even more so if the shunt resistor is wire-wound, not the bar/metal film type).]
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